The IP strategy for semiconductor startups that holds value in 2026 files on what a competitor's shipped product reveals and keeps everything else as a trade secret. Detectability, not novelty, sets the price of a chip patent. A claim nobody can read off a packaged die, a datasheet, or a standard interface transaction is a public disclosure with no enforcement behind it.
Investors have put roughly $10.7 billion into semiconductor startups so far in 2026, with 18 companies taking rounds above $100 million in Q1 alone. Etched closed a $300 million Series C on 23 July. MatX reached $605 million across three rounds. Almost every one of those decks lists a patent count. Very few of those patents could survive the question an acquirer asks in year four: show me the product you can prove infringes this.
The reason most chip patents never get enforced
Finnegan, one of the largest patent firms in the United States, puts the mechanic bluntly in its guidance on drafting and enforcing semiconductor patents: proving that device and fabrication inventions are being used by others normally requires reverse engineering, which is costly, slow, and may not even show the invention is in use. A nanoscale multilayer device can demand repeated cross sectional SEM and TEM analysis with metal layers etched away one at a time. The bill starts in the tens of thousands of dollars and climbs from there, and it buys a maybe.
Now put that against the disclosure clock. Under 35 U.S.C. 122(b) your application publishes 18 months after its earliest priority date, on time, every time, whether or not the claim is ever enforceable. So a startup that patents its analog calibration trick has bought a guaranteed lesson for its competitor and an optional remedy for itself. The teaching is certain. The protection is a coin flip that costs six figures to flip.
That asymmetry is the whole game in silicon, and it is the reason the vertical IP playbooks that work elsewhere transfer badly. Software infringement is visible in an API response. Robotics infringement shows up in observed machine behaviour, which is why the IP strategy for robotics startups puts its weight on the control layer. A transistor level trick is buried under 15 metal layers in an epoxy package.
The Semiconductor Detectability Ladder
Rank every claim before it is drafted, not after it is filed. Four rungs, ordered by what it costs an opponent to prove use.
Tier 1, visible in the datasheet. Instruction set extensions, register maps, protocol behaviour, power state transitions, interface timing, error handling sequences. Proof of infringement is a document and a test bench. File aggressively here, because the evidence is free.
Tier 2, visible in the package. Die stacking order, interposer topology, chiplet partitioning, through silicon via arrangement, thermal structures. X-ray and CT imaging resolve most of it for a few thousand dollars, without decapping. File here.
Tier 3, visible in the die at cost. Metal routing, macro placement, memory array organisation, cell level structures. Worth filing only when the claim reads on a high volume part where a single enforcement campaign pays for the analysis several times over. One or two of these, chosen deliberately, beats twenty filed on reflex.
Tier 4, not visible at all. Analog trim and calibration routines, firmware embedded compensation, process recipes, yield tuning, test escape screens, binning logic. These belong in a trade secret programme with access logs and exit protocols, never in an application. If they are already drafted, a nonpublication request under 35 U.S.C. 122(b)(2)(B)(i) keeps them out of the public record, at the cost of surrendering foreign filing rights. That trade is usually worth it for a recipe that no examiner in Shenzhen needs to read. Our note on how to value trade secrets covers what those assets are worth once they sit off the patent record.
Chiplet standards quietly repriced the whole portfolio
The chiplet interconnect market passed $2.17 billion in 2025 and is compounding at 34.4% through 2035, with the open standard segment led by UCIe growing fastest at 36.7%. UCIe 3.0 landed in August 2025 and production parts are following.
Here is the part almost nobody has priced in. A standard interface is, by construction, documented and externally observable. Any behaviour a compliant chiplet must exhibit on a UCIe link can be captured with a protocol analyser by an engineer who has never seen your layout. Claims written at that boundary jump from Tier 3 or Tier 4 straight to Tier 1. Designers got easier integration out of the standardisation wave. Patent owners got something bigger: the enforceability line moved, and it moved in favour of whoever files at the interface first.
Two cautions. Declaring a patent essential to a standard pulls you into FRAND commitments and rate setting, which is a different business with different economics, covered in our breakdown of SEP licensing and FRAND. For most startups the better position is standard adjacent: claims that read on how a compliant implementation achieves the required behaviour, without being necessary to comply. Second, interface claims age with the specification, so the continuation strategy matters more than the parent.
Two instruments founders leave on the table
Mask work registration. The Semiconductor Chip Protection Act, 17 U.S.C. 901 and following, protects the topography of the chip itself through registration with the Copyright Office. Ten year term, registration fee measured in hundreds of dollars, and it covers exactly the copying case that is easiest to prove: someone lifted the layout. It is close to free relative to a patent family and most fabless startups have never filed one.
The foundry and OSAT agreement. Process development kits, co-developed process steps, test programmes, and the yield data generated across every wafer lot pass through contracts written by the counterparty's lawyers. Improvement clauses and grantbacks routinely hand the fab a licence to what your team learned tuning its process. Yield and test data is a compounding operational asset, which is the same distinction we draw in living data versus static datasets. Negotiate ownership of derived process and test data before tape out, when you still have something the fab wants.
The 90 day sequence
Five moves, in order.
One, score every pending and drafted claim against the four rungs. Expect 40% to 60% of a first time portfolio to sit at Tier 4. Two, pull the Tier 4 claims before their publication date and move them into a documented trade secret programme. Three, redraft Tier 3 claims toward the observable result the circuit produces rather than the circuit that produces it, so the claim chart can be built from a bench measurement. Four, map the remaining filings against the interface standards roadmap and file at the boundaries your parts will speak in 24 to 36 months. Five, register mask works for every taped out design and fix the improvement and derived data clauses in the foundry, OSAT, and IP vendor agreements.
The output is a smaller portfolio that prices higher. That is the direction of travel across the market: structured IP positions carry a measurable multiple premium, which we quantified in the 41% valuation gap between audited and unaudited portfolios.
Frequently asked questions
Should a fabless semiconductor startup patent its circuit design?
Only where the circuit's behaviour shows up outside the package. If proving use would require decapping, delayering, and TEM imaging of a competitor's die, the patent buys a public disclosure at 18 months and an enforcement path that costs tens of thousands of dollars with no guarantee of a result. Those designs are better protected as trade secrets.
What is the biggest IP mistake semiconductor startups make?
Filing on the hardest engineering rather than the most provable engineering. The two are rarely the same claim. The cleverest thing your team built is usually the thing buried deepest in the die, which makes it the worst patent and the best trade secret.
How do investors value semiconductor IP in 2026?
By provability and position, not count. The questions in diligence are which claims read on a shipped competitor product, what the evidence path is, whether the foundry agreement leaks improvements, and whether filings sit at the interface standards the market is consolidating around. A hundred undetectable filings score below eight enforceable ones.
Do trade secrets work for chip companies given employee mobility?
They work when they are administered. Access controls, logged disclosure, marked documents, exit interviews, and clean room boundaries with contractors. An undocumented secret is not a secret in litigation, it is an allegation. The programme is the asset.
When should a chip startup file at an interface standard boundary?
Before the specification version your product will ship against is finalised, which in practice means 18 to 30 months ahead of the part. Standard adjacent claims filed after everyone has implemented are design arounds waiting to happen.
Where this leaves you
Chip startups are raising more capital than at any point in the last decade and filing portfolios that will not survive a diligence question. The fix is not more filings. It is scoring what you already have against what an opponent can actually see, then moving each claim to the instrument that fits it.
Beyond Elevation runs that scoring for technology companies, from the claim by claim detectability audit through to the licensing programme it supports. If you are taping out in the next four quarters or heading into a raise with a patent count on slide 11, get the portfolio audited before the number gets tested.